1. Field
The embodiments relate to semiconductor memory devices capable of detecting whether a short circuit has occurred between data bus lines.
2. Description of the Related Art
In a semiconductor memory device, a memory cell array and external input/output terminals or other internal logical circuits are connected to each other with a plurality of data bus lines therebetween. The memory cell array includes a plurality of word lines, a plurality of bit lines, and memory cells arranged in portions where the plurality of word lines and the plurality of bit lines intersect with each other. In accordance with the layout of components constituting a chip, that is, in the case where the wire lengths of the data bus lines are increased a short circuit failure caused by a manufacturing process may occur between adjacent data bus lines.
By writing a specific data pattern into memory cells and reading the specific data pattern in a performance test process, such a short circuit failure between data bus lines can be detected. The data pattern to be written is selected in such a manner that data items having different levels (that is, a data item at level HI and a data item at level L or a data item at level L and a data item at level H) are output to adjacent data bus lines.
However, in the case of carrying out the above-mentioned performance test, a process for writing data must be performed. In addition, after the performance test is carried out, a process for deleting data must be performed. In particular, since a memory device, such as a flash memory device, including an electrically erasable programmable read-only memory (EEPROM) serving as a memory cell, which requires a relatively long time to perform the writing process and the deleting process, the throughput of the performance test is reduced.
In order to solve the above-described problem, technology described in Japanese Patent Laid-Open No. 7-192500 is available. According to the technology, a test circuit for floating a word line or the like for which a short-circuit check is to be performed and for applying a reference voltage is provided.
In addition, technology described in Japanese Patent Laid-Open No. 2000-195300 is available. According to the technology, mask read-only memories (ROMs) are added to bit lines within a memory cell array and a data pattern of data items for short circuit testing is written to the mask ROMs. Thus, by selecting mask ROM memory cells and outputting a data pattern of data items for testing bit lines in a short circuit failure detection test process, a detection whether a short circuit failure has occurred between the data bus lines can be performed by outputting different data items to adjacent data bus lines and determining whether the data outputs are the same as the expected values.